1. Field of the Invention
The present invention relates to a semiconductor device which has high off-breakdown-voltage and low on-resistance.
2. Description of the Background Art
FIG. 1 is a cross sectional view of a conventional double diffused MOSFET transistor (VDMOS transistor). In the VDMOS transistor, an N.sup.- type semiconductor layer 2 is formed on an N.sup.+ type semiconductor substrate 1. The N.sup.- type semiconductor layer 2 includes P type well regions 3 each including N.sup.+ type source regions 4. The P type well regions 3 and the N.sup.+ type source regions 4 are created by ion implantation; for example, boron-implantation to create the P type well regions 3 and arsenic-implantation to create the N.sup.+ type source regions 4. A gate oxide film 6, a gate electrode 5 , a source electrode 7 and an oxide film 6 are formed on the N.sup.- type semiconductor layer 2. A drain electrode 8 is disposed on the bottom major surface of the semiconductor substrate 1.
Thus, the device of FIG. 1 is an N-channel VDMOS transistor. When the source electrode 7 and the gate electrode 5 are commonly at low potential and the drain electrode 8 is at high potential, the P type well region 3 immediately under the gate electrode 5 does not invert into N type. Hence, the semiconductor layer 2 comprises a depletion layer extending from a PN junction between the well region 3 and the semiconductor layer 2 toward the semiconductor substrate 1. In the conventional N-channel VDMOS transistor, the growing depletion layer reaches the semiconductor substrate 1, thereby breakdown voltage being maintained (OFF state).
When voltage applied to the gate electrode 5 is changed so that the gate electrode 5 is at higher potential than the source electrode 7, the P type well region 3 immediately under the gate electrode 5 inverts into N type. Hence, electron flow is allowed from the source region 4 to the semiconductor substrate 1 through the N-inverted portion (ON state).
It is known that on-resistance primarily depends on resistance at N-inverted portion of the well region 3, i.e., channel resistance, JFET resistance, which is created between neighboring well regions 3, and resistance of the semiconductor layer 2. Although the resistance of the semiconductor layer 2 decreases with an increase in its impurity concentration and a decrease in its thickness, too small thickness and too high impurity concentration must be avoided. Too small thickness leads to deterioration in breakdown voltage while too high impurity concentration hinders a depletion layer from growing as desired. Thus, high breakdown voltage and low resistance of the semiconductor layer 2 are just not compatible: high breakdown voltage is ensured only in return of an insufficient reduction the resistance of the semiconductor layer 2, i.e., at the expense of low on-resistance.
Decreased channel resistance and decreased JFET resistance are possible if process patterns have refined features, in other words, if diffusion profiles of the well region 3 and the source region 4 are optimal. However, this also has disadvantages. When the process patterns become refined, the gate electrode 5 and the source electrode 7 short-circuit due to degraded insulation therebetween, with a result that a yield drops. In addition, it becomes difficult to form the source electrode 7 because the source electrode 7 needs to contact both the well region 3 and the source region 4.